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Sheet目录3873

124页 125页 126页 127页 [128页]129页 130页 131页 132页

dsPIC30F1010/202X

DS70178C-page 212

Preliminary

2006 Microchip Technology Inc.

FIGURE 18-10:

TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

18.7.1.1

POR with Long Crystal Start-up Time

(with FSCM Enabled)

The oscillator start-up circuitry is not linked to the POR

circuitry.

Some

crystal

circuits

(especially

low

frequency crystals) will have a relatively long start-up

time. Therefore, one or more of the following conditions

is possible after the POR timer and the PWRT have

expired:

The oscillator circuit has not begun to oscillate.

The Oscillator Start-up Timer has NOT expired (if

a crystal oscillator is used).

The PLL has not achieved a LOCK (if PLL is

used).

If the FSCM is enabled and one of the above conditions

is true, then a clock failure trap will occur. The device

will automatically switch to the FRC oscillator and the

user can switch to the desired crystal oscillator in the

trap, ISR.

18.7.1.2

Operating without FSCM and PWRT

If the FSCM is disabled and the Power-up Timer

(PWRT) is also disabled, then the device will exit rap-

idly from Reset on power-up. If the clock source is FRC

or EC, it will be active immediately.

If the FSCM is disabled and the system clock has not

started, the device will be in a frozen state at the Reset

vector until the system clock starts. From the user’s

perspective, the device will appear to be in Reset until

a system clock is available.

FIGURE 18-11:

EXTERNAL POWER-ON

RESET CIRCUIT (FOR

SLOW VDD POWER-UP)

VDD

MCLR

Internal POR

PWRT Time-out

OST Time-out

Internal Reset

TPWRT

TOST

Note:

Dedicated supervisory devices, such as

the MCP1XX and MCP8XX, may also be

used as an external Power-on Reset

circuit.

Note 1: External Power-on Reset circuit is

required only if the VDD power-up slope

is too slow. The diode D helps discharge

the capacitor quickly when VDD powers

down.

2: R should be suitably chosen so as to

make sure that the voltage drop across

R does not violate the device’s electrical

specification.

3: R1 should be suitably chosen so as to

limit any current flowing into MCLR from

external capacitor C, in the event of

MCLR/VPP pin breakdown due to Elec-

trostatic Discharge (ESD) or Electrical

Overstress (EOS).

VDD

dsPIC30F

MCLR

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